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19-4623; rev 0; 5/09 product specification crimzon ? zlr32300 z8 ? ? low-voltage rom mcu with infrared timers maxim integrated products inc. 120 san gabriel drive, sunnyvale ca 94086 downloaded from: http:///
ps022613-0409 maxim integrated products 120 san gabriel drive sunnyvale, ca 94086 united states 408-737-7600 www.maxim-ic.com copyright ? 2009 maxim integrated products maxim cannot assume responsibility for use of any circuitry other than circuitry ent irely embodied in a maxim product. maxim re tains the right to make changes to its products or specifications to improve performance, reliability or manufacturability. all infor mation in this document, including descriptions of f eatures, functions, performance, technical specifications and avai lability, is subjec t to change without notice at any time. while the information furnished herein is held to be accurate and reliable, no responsibilit y will be assumed by maxim for its use. furthermore, the information contained herein does not c onvey to the purchaser of microelectronic devices any license under the pat ent right of any manufacturer. maxim is a registered trademark of maxim integrated products, inc. all other products or service names used in this publication are for identification pur poses only, and may be trademarks or reg istered trademarks of their respective companies. all other trademarks or registered trademarks mentioned herein are the property of th eir respective holders. z8 is a registered trademark of zilog, inc. crimzon is a registered trademark of universal electronics inc. downloaded from: http:///
crimzon ? zlr16300 product specification ps022613-0409 revision history iii revision history each instance in the revision history table reflects a change to this document from its previous revision. for more details, refer to the corresponding pages and appropriate links in the table below. date revision level description page number april 2009 13 changed to maxim product all february 2008 12 updated the ordering information section. 92 january 2008 11 updated the ordering information section. 92 august 2007 10 updated the disclaimer section and implemented style guide. all february 2007 09 updated low-voltage detection register lvd(d)0ch . 60 may 2006 08 added pin 22 to smr block input, figure 32 . 54 december 2005 07 updated section clock and input/output port. 50, 14 downloaded from: http:///
crimzon ? zlr16300 product specification 19-4623; rev 0; 5/09 table of contents iv table of contents architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 development features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 xtal1 crystal 1 (time-based input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 xtal2 crystal 2 (time-based output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 reset (input, active low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 program memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 expanded register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 register file . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 counter/timer functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 port configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 stop mode recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 watchdog timer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 low-voltage detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 expanded register file control registers (0d) . . . . . . . . . . . . . . . . . . . . . . 62 expanded register file control registers (0f) . . . . . . . . . . . . . . . . . . . . . . 69 standard control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 standard test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 part number description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 downloaded from: http:///
crimzon ? zlr16300 product specification 19-4623; rev 0; 5/09 table of contents v index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 customer support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 architectural overview 1 architectural overview maxims crimzon ? zlr32300 is an rom-based member of the mcu family of infrared microcontrollers. with 237 b of general-purpose ram and 4 kb to 32 kb of rom, cmos microcontrollers offer fast-executing, efficient use of memory, sophisticated interrupts, input/output (i/o ) bit manipulation capabilities, automated pulse generation/reception, and internal key-scan pull-up transistors. the crimzon zlr32300 architecture (see figure 1 on page 4) is based on maxims 8-bit microcontroller core with an expanded register file allowing access to register-mapped peripherals, i/o circuits, and powerful counter/timer circuitry. the z8 ? offers a flexible i/o scheme, an efficient register and address space structure, and a number of ancillary features that are useful in many consumer, automotive, computer peripheral, and battery-operated hand-held applications. there are three basic address spaces available to support a wide range of configurations: 1. program memory 2. register file 3. expanded register file the register file is composed of 256 bytes of ram. it includes four i/o port registers, 16 control and status registers, and 236 general-purpose registers. the expanded register file consists of two additional register groups (f and d). to unburden the program from coping with such real-time problems as generating complex waveforms or receiving and demodulating complex waveform/pulses, the crimzon zlr32300 offers a new intelligent counter/timer architecture with 8-bit and 16-bit counter/timers (see figure 2 on page 5). also included are a large number of user-selectable modes and two on-board co mparators to process analog signals with separate reference voltages. all signals with an overline, , are active low. for example, b/w , in which word is active low, and b /w, in which byte is active low. power connections use the conventional descriptions listed in table 1. note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 architectural overview 2 development features table 2 lists the features of crimzon zlr32300 family. the development features of crimzon zlr32300 include: low power consumptionC5 mw (typical) three standby modes: C stop1.4 ? a (typical) C halt0.5 ma (typical) C low voltage special architecture to automa te generation and reception of complex pulses or signals: C one programmable 8-bit counter/timer wi th two capture registers and two load registers C one programmable 16-bit counter/timer with one 16-bit capture register pair and one 16-bit load register pair C programmable input glitch filter for pulse reception six priority interruptsC three external C two assigned to counter/timers C one low-voltage detection interrupt low-voltage detection and high-voltage detection flags programmable watchdog timer/power-on reset (wdt/por) circuits two independent comparators with programmable interrupt polarity table 1. power connections connection circuit device power v cc v dd ground gnd v ss table 2. crimzon zlr32300 family features device rom (kb) ram* (bytes) i/o lines voltage range crimzon zlr32300 4, 8, 16, 24, 32 237 32, 24 or 16 2.0C3.6 v *general purpose downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 architectural overview 3 mask selectable pull-up transi stors on ports 0, 1, 2, 3 rom optionsC port 0: 0C3 pull-up transistors C port 0: 4C7 pull-up transistors C port 1: 0C3 pull-up transistors C port 1: 4C7 pull-up transistors C port 2: 0C7 pull-up transistors C port 3: 0C3 pull-up transistors C wdt enabled at por downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 architectural overview 4 functional block diagram figure 1 displays the zlr32300 mcu functional block diagram. figure 1. functional block diagram z8? core port 2 port 0 p21p22 p23 p24 p25 p26 p27 p20 i/o bit programmable p04p05 p06 p07 p00 p01 p02 p03 i/o nibble programmable register file 256 x 8-bit register bus internal address bus internal data bus expanded register file expanded register bus z8 core counter/timer 8 8-bit counter/timer 16 16-bit v dd v ss xtal reset pref1/p30 p31 p32 p33 p34 p35 p36 p37 port 3 machine timing & instruction control power 4 4 rom up to 32k x 8 port 1 p14 p15 p16 p17 p10p11 p12 p13 i/o byte programmable 8 watchdog timer low-voltage detection high-voltage detection power-on reset note: refer to the specific package for available pins. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 architectural overview 5 figure 2. counter/timers diagram hi16 lo16 tc16h tc16l hi8 lo8 tc8l 8 8 16 8 input sclk timer 16 timer 8/16 timer 8 8 8 8 8 8 16-bit t16 clock divider glitch filter edge detect circuit 8-bit t8 tc8h 1248 and/or logic downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 6 pin description the pin configuration for the 20-pin pdip/soic/ssop is displayed in figure 3 and described in table 3. the pin configurati on for the 28-pin pdip/soic/ssop is dis- played in figure 4 on page 7 and described in table 4 on page 7. the pin configu- rations for the 48-pin ssop versions are displayed in figure 5 on page 8 and described in table 5 on page 8. figure 3. 20-pin pdip/soic/ssop pin configuration table 3. 20-pin pdip/soic/ssop pin identification pin no symbol function direction 1C3 p25Cp27 port 2, bits 5,6,7 input/output 4 p07 port 0, bit 7 input/output 5v dd power supply 6 xtal2 crystal oscillator clock output 7 xtal1 crystal oscillator clock input 8C10 p31Cp33 port 3, bits 1,2,3 input 11,12 p34, p36 port 3, bits 4,6 output 13 p00/pref1/p30 port 0, bit 0/analog reference input port 3 bit 0 input/output for p00 input for pref1/p30 14 p01 port 0, bit 1 input/output 15 v ss ground 16C20 p20Cp24 port 2, bits 0,1,2,3,4 input/output p25p26 p27 p07 v dd xtal2 xtal1 p31p32 p33 p24p23 p22 p21 p20 v ss p01p00/pref1/p30 p36 p34 12 3 4 5 6 7 8 9 10 2019 18 17 16 15 14 13 12 11 20-pin pdip soic ssop downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 7 figure 4. 28-pin pdip/soic/ssop pin configuration table 4. 28-pin pdip/soic/ssop pin identification pin symbol direction description 1-3 p25-p27 input/output port 2, bits 5,6,7 4-7 p04-p07 input/output port 0, bits 4,5,6,7 8v dd power supply 9 xtal2 output crystal, oscillator clock 10 xtal1 input crystal, oscillator clock 11-13 p31-p33 input port 3, bits 1,2,3 14 p34 output port 3, bit 4 15 p35 output port 3, bit 5 16 p37 output port 3, bit 7 17 p36 output port 3, bit 6 18 pref1/p30 port 3 bit 0 input analog ref input; connect to v cc if not used input for pref1/p30 19-21 p00-p02 input/output port 0, bits 0,1,2 22 v ss ground 23 p03 input/output port 0, bit 3 24-28 p20-p24 input/output port 2, bits 0-4 p24p23 p22 p21 p20 p03 v ss p02p01 p00 pref1/p30 p36 p37 p35 p25p26 p27 p04 p05 p06 p07 v dd xtal2xtal1 p31p32 p33 p34 1 14 2815 28-pin pdip soic ssop downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 8 figure 5. 48-pin ssop pin configuration table 5. 48-pin configuration 48-pin ssop no symbol 31 p00 32 p01 35 p02 41 p03 5p 0 4 7p 0 5 8p 0 6 11 p07 33 p10 34 p11 nc p25p26 p27 p04 n/c p05p06 p14 p15 p07 vddvdd n/c p16p17 xtal2 xtal1 p31p32 p33 p34 nc vss ncnc p24 p23 p22 p21 p20 p03 p13 p12 vss vss n/c p02 p11 p10 p01 p00 n/c pref1/p30 p36 p37 p35 reset 48-pin ssop 1 23 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 24 4847 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 9 39 p12 40 p13 9p 1 4 10 p15 15 p16 16 p17 42 p20 43 p21 44 p22 45 p23 46 p24 2p 2 5 3p 2 6 4p 2 7 19 p31 20 p32 21 p33 22 p34 26 p35 28 p36 27 p37 23 nc 47 nc 1n c 25 reset 18 xtal1 17 xtal2 12, 13 v dd 24, 37, 38 v ss 29 pref1/p30 48 nc 6n c table 5. 48-pin configuration (continued) 48-pin ssop no symbol downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 10 14 nc 30 nc 36 nc table 5. 48-pin configuration (continued) 48-pin ssop no symbol downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 11 pin functions xtal1 crystal 1 (time-based input) this pin connects a parallel-resonant crystal or ceramic resonator, to the on-chip oscillator input. additionally, an optional ex ternal single-phase clock can be coded to the on-chip oscillator input. xtal2 crystal 2 (time-based output) this pin connects a parallel-resonant, crysta l or ceramic resonant to the on-chip oscillator output. input/output ports the cmos input buffer for each port 0, 1, or 2 pin is always connected to the pin, even when the pin is configured as an output. if the pin is configured as an open-drain output and no external signal is applied, a high output state can cause the cmos input buffer to float. this might lead to excessive leakage current of more than 100 ? a. to prevent this leakage, connect the pin to an external signal with a defined logic level or ensure its output state is low, especially during stop mode. internal pull-ups are disabled on any given pin or group of port pins when programmed into output mode. port 0, 1, and 2 have input and output capability. the input logic is always present no matter whether the port is configured as input or output. when doing a read instruction, the mcu reads t he actual value at the input logic but not from the output buffer. in addition, the instructions of or, and, and xor have the read-modify- write sequence. the mcu first reads the port, and then modifies the value and load back to the port. precaution must be taken if the port is configured as open- drain output or if the port is driving any circuit that makes the voltage different from the desired output logic. for example, pins p00Cp07 are not connected to anything else. if it is configured as open-drain output with output logic as caution: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 12 one, it is a floating port and reads back as zero. the following instruction sets p00-p07 all low. and p0,#%f0 port 0 (p07Cp00) port 0 is an 8-bit, bidirectional, cmos-c ompatible port. these eight i/o lines are configured under software control as a nibble i/o port. the output drivers are push-pull or open-drain controlled by bit d2 in the pcon register. if one or both nibbles are needed for i/o operation, they must be configured by writing to the port 0 mode register. after a hardware reset, port 0 is configured as an input port. an optional pull-up transistor is available as a mask option on all port 0 bits with nibble select. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 13 the port 0 direction is reset to be input following an stop mode recovery. figure 6. port 0 configuration port 1 (p17Cp10) port 1 (see figure 7 ) can be configured for standard port input or output mode. after por, port 1 is configured as an input port. the output drivers are either push-pull or open-drain and are controlled by bit d1 in the pcon register. note: zlr32300 rom 44 port 0 (i/o) open-drain i/o out in v cc pad mask option resistive transistor pull-up downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 14 the port 1 direction is reset to be input following an smr. in 20- and 28-pin packages, port 1 is reserved. a write to this register will have no effect and will always read ff. figure 7. port 1 configuration port 2 (p27Cp20) port 2 is an 8-bit, bidirectional, cmos-compatible i/o port (see figure 8 on page 15). these eight i/o lines can be independently configured under software control as inputs or outputs. port 2 is always av ailable for i/o operation. a mask option is available to connect eight pull-up transisto rs on this port. bits programmed as out- puts are globally programmed as either push-pull or open-drain. the por resets with the eight bits of port 2 configured as inputs. note: zlr32300 rom 8 port 1 (i/o) open-drain oen out in mask option v cc resistive transistor pull-up pad downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 15 port 2 also has an 8-bit input or and and gate, which can be used to wake up the part. p20 can be programmed to ac cess the edge-detection circuitry in demodulation mode. figure 8. port 2 configuration port 3 (p37Cp30) port 3 is a 8-bit, cmos-compatible fixed i/o port (see figure 9 on page 16). port 3 consists of four fixed input (p33Cp30) and four fixed output (p37Cp34), which can be configured under software control for interrupt and as output from the counter/ timers. p30, p31, p32, and p33 are standard cmos inputs; p34, p35, p36, and p37 are push-pull outputs. zlr32300 rom port 2 (i/o) pad in out i/o open-drain resistive transistor pull-up v cc mask option downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 16 figure 9. port 3 configuration two on-board comparators process analog signals on p31 and p32, with reference to the voltage on pref1 and p33. the analog function is enabled by programming the port 3 mode register (b it 1). p31 and p32 are programmable as rising, falling, or both edge triggered interrupts (irq register bits 6 and 7). pref1 and p33 are the comparator reference voltage inputs. access to the counter timer edge-detection circuit is through p31 or p20 (see t8 and t16 common func- - zlr32300 rom port 3 (i/o) p32 (an2) p31 (an1) pref1 from stop mode recovery source of smr p33 (ref2) irq2, p31 data latch pref1/p30 p31 p32 p33 p34 p35 p36 p37 d1 1 = analog 0 = digital r247 = p3m + - + irq0, p32 data latch i rq1, p33 data latch comp1 comp2 dig. an. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 17 tionsctr1(0d)01h on page 30). other edge detect and irq modes are described in table 6. comparators are powered down by entering stop mode. for p31Cp33 to be used in a smr source, these inputs must be placed into digital mode. 2 port 3 also provides output for each of the counter/timers and the and/or logic (see figure 10 on page 18). control is performed by programming bits d5Cd4 of ctr1, bit 0 of ctr0, and bit 0 of ctr2. table 6. port 3 pin function summary pin i/o counter/timers comparator interrupt pref1/p30 in rf1 p31 in in an1 irq2 p32 in an2 irq0 p33 in rf2 irq1 p34 out t8 ao1 p35 out t16 p36 out t8/16 p37 out ao2 p20 i/o in note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 18 figure 10. port 3 counter/timer output configuration pad p34 comp 1 v dd mux pcon, d0 mu x ctr0, d0 p31 p30 (pref 1) p34 data t8_out + pad p35 v dd mux ctr2, d0 out 35 t16_out pad p36 v dd mux ctr1, d6 out 36 t8/t16_out pad p37 v dd mux pcon, d0 p37 data - p31 p3m d1 comp 2 p32 p33 + - p32 p3m d1 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 pin description 19 comparator inputs in analog mode, p31 and p32 have a comparator front end. the comparator reference is supplied to p33 and pref1. in this mode, the p33 internal data latch and its corresponding irq1 are diverted to the smr sources (excluding p31, p32, and p33) as displayed in figure 9 on page 16. in digital mode, p33 is used as d3 of the port 3 input register, which then generates irq1. comparators are powered down by entering stop mode. for p31Cp33 to be used in a smr source, these inputs must be placed into digital mode. comparator outputs these channels can be programmed to be output on p34 and p37 through the pcon register. reset (input, active low) reset initializes the mcu and is accomplished either through power-on, watch- dog timer, stop mode recovery, low-voltage detection, or external reset. during power-on reset and watchdog timer reset, the internally generated reset drives the reset pin low for the por time. any devices driving the external reset line must be open-drain to avoid damage from a possible conflict during reset condi- tions. pull-up is provided internally. when the zlr32300 asserts (low) the reset pin, the internal pull-up is dis- abled. the zlr32300 does not assert the reset pin when under vbo. the external reset does not initiate an exit from stop mode. note: note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 20 functional description this device incorporates spec ial functions to enhance the z8 ? functionality in con- sumer and battery-operated applications. program memory this device addresses 32 kb of rom memory. the first 12 bytes are reserved for interrupt vectors. these locations contain the six 16-bit vectors that correspond to the six available interrupts (see figure 11 on page 21). ram this device features 256 b of ram. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 21 figure 11.program memory map (32 k rom) expanded register file the register file has been expanded to al low for additional system control regis- ters and for mapping of additional peripher al devices into the register address area. the z8 register address space (r 0 through r15) has been implemented as 16 banks, with 16 registers per bank. thes e register groups are known as the on-chip rom reset start address irq5irq5 irq4 irq4 irq3 irq3 irq2 irq2 irq1 irq1 irq0 irq0 1211 10 9 8 7 6 5 4 3 2 1 0 32768 location of first byte of instruction executed after reset interrupt vector (lower byte) interrupt vector (upper byte) not accessible downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 22 erf (expanded register file). bits 7C4 of register rp select the working register group. bits 3C0 of register rp select the expanded register file bank. an expanded register bank is also referred to as an expanded register group (see figure 12 on page 23). note: note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 23 figure 12. expanded register file architecture uuuuuuu0 00000000 00000000 00000000 00 0f 7f f0 ff ff spl 00000000 uuuuuuuu 00000000 uuuuuuuu uuuuuuuu uuuuuuuu 11111111 00000000 11001111 uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu uuuuuuuu fe sph fd rp fc flags fb imr fa irq f9 ipr f8 p01m f7 p3m f6 p2m f5 reserved f4 reserved f3 reserved f2 reserved f1 reserved f0 reserved d7 d6 d5 d4 d3 d2 d1 d0 uu001101 u01000u0 11111110 (f) 0f wdtmr (f) 0e reserved (f) 0d smr2 (f) 0c reserved (f) 0b smr (f) 0a reserved (f) 09 reserved (f) 08 reserved (f) 07 reserved (f) 06 reserved (f) 05 reserved (f) 04 reserved (f) 03 reserved (f) 02 reserved (f) 01 reserved (f) 00 pcon 76543210 expanded register bank pointer working register uuuuuuuu uuuuuuuu 00000000 (d) 0c lvd (d) 0b hi8 (d) 0a lo8 (d) 09 hi16 (d) 08 lo16 (d) 07 tc16h (d) 06 tc16l (d) 05 tc8h (d) 04 tc8l (d) 03 ctr3 (d) 02 ctr2 (d) 01 ctr1 (d) 00 ctr0 group pointer register file (bank 0)** 00011111 ** 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 u = unknown * not reset with a stop mode recovery. p1 reserved in 20 and 28-pin package. ** all addresses are in hexadecimal ? is not reset with a stop mode recovery, except bit 0 ?? bit 5 is not reset with a stop mode recovery ??? bits 5,4,3,2 not reset with a stop mode recovery ???? bits 5 and 4 not reset with a stop mode recovery ????? bits 5,4,3,2,1 not reset with a stop mode recovery expanded reg. bank 0/group (0) * (0) 03 p3 (0) 02 p2 (0) 01 p1 (0) 00 p0 0 u u u u ????? ???? ??? ?? ** * * * * * * * ** expanded reg. bank f/group 0** expanded reg. bank 0/group 15** register pointer z8 ? standard control registers expanded reg. bank d/group 0 ? reset condition downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 24 the upper nibble of the register pointer (see figure 13 ) selects which working register group of 16 bytes in the register file, is accessed out of the possible 256. the lower nibble selects the expanded register file bank and, in the case of the crimzon zlr32300 family, banks 0, f, and d are implemented. a 0h in the lower nibble allows the normal register file (bank 0) to be addressed. any other value from 1h to fh exchanges the lower 16 registers to an expanded register bank. figure 13. register pointer example : crimzon zlr32300 (see figure 12 on page 23). r253 rp = 00h r0 = port 0 r1 = port 1 r2 = port 2 r3 = port 3 but if: r253 rp = 0dh r0 = ctr0 r1 = ctr1 r2 = ctr2 r3 = ctr3 the counter/timers are mapped into erf group d. access is easily performed using the following: ld rp, #0dh ; select erf d for access to bank d ; (working register group 0) ld r0,#xx ; load ctr0 ld 1, #xx ; load ctr1 r253 rp d7 d6 d5 d4 d3 d2 d1 d0 expanded register file pointer working register pointer default setting after reset = 0000 0000 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 25 ld r1, 2 ; ctr2 ? ctr1 ld rp, #0dh ; select erf d for access to bank d ; (working register group 0) ld rp, #7dh ; select expanded register bank d and working ; register group 7 of bank 0 for access. ld 71h, 2 ; ctr2 ? register 71h ld r1, 2 ; ctr2 ? register 71h register file the register file (bank 0) consists of 4 i/o port registers, 237 general-purpose reg- isters, 16 control and status registers (r0Cr3, r4Cr239, and r240Cr255, respectively), and two expanded registers groups in banks d (see table 7 on page 28) and f. instructions can access registers directly or indirectly through an 8-bit address field, thereby allowing a sh ort, 4-bit register address to use the reg- ister pointer (see figure 14 on page 26). in the 4-bit mode, the register file is divided into 16 working register groups, each occupying 16 continuous locations. the register pointer addresses the starting lo cation of the active working register group. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 26 working register group e0Cef can only be accessed through working registers and indirect addressing modes. figure 14. register pointerdetail stack the internal register file is used for the stack. an 8-bit stack pointer spl (r255) is used for the internal stack that resides in the general-purpose registers (r4C r239). sph (r254) can be used as a general-purpose register. timers t8_capture_hihi8(d)0bh this register holds the captured data from the output of the 8-bit counter/timer0. typically, this register holds the number of counts when the input signal is 1. field bit position description t8_capture_hi [7:0] r/w captured datano effect note: r 7 r 6 r 5 r 4 r 3 r 2 r 1 r 0 the upper nibble of the register file address provided by the register pointer specifies the active working-register group. specified working register group register group 1 register group 0 i/o ports r253 the lower nibble of the register file address provided by the instruction points to the specified register. * rp = 00: selects register bank 0, working register group 0 r15 to r0 r15 to r4 * r3 to r0 * fff0 ef e0 df d0 40 3f 30 2f 20 1f 10 0f 00 register group 2 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 27 t8_capture_lol08(d)0ah this register holds the captured data from the output of the 8-bit counter/timer0. typically, this register holds the number of counts when the input signal is 0. t16_capture_hihi16(d)09h this register holds the captured data from the output of the 16-bit counter/ timer16. this register holds the ms-byte of the data. t16_capture_lol016(d)08h this register holds the captured data from the output of the 16-bit counter/ timer16. this register holds the ls-byte of the data. counter/timer2 ms-byte hold registertc16h(d)07h counter/timer2 ls-byte hold registertc16l(d)06h field bit position description t8_capture_l0 [7:0] r/w captured datano effect field bit position description t16_capture_hi [7:0] r/w captured datano effect field bit position description t16_capture_lo [7:0] r/w captured datano effect field bit position description t16_data_hi [7:0] r/w data field bit position description t16_data_lo [7:0] r/w data downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 28 counter/timer8 high hold registertc8h(d)05h counter/timer8 low hold registertc8l(d)04h ctr0 counter/timer8 control registerctr0(d)00h table 7 lists and briefly describes the fields for this register. field bit position description t8_level_hi [7:0] r/w data field bit position description t8_level_lo [7:0] r/w data table 7. ctr0(d)00h counter/timer8 control register field bit position value description t8_enable 7------- r/w 0* 10 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------- r/w 0* 1 modulo-n single pass time_out --5------ r/w 0** 10 1 no counter time-out counter time-out occurred no effect reset flag to 0 t8 _clock ---43--- r/w 0 0** 0 11 0 1 1 sclksclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0** 1 disable data ca pture interrupt enable data capture interrupt counter_int_mask ------1- r/w 0** 1 disable time-o ut interrupt enable time-out interrupt p34_out -------0 r/w 0* 1 p34 as port output t8 output on p34 *indicates the value upon power-on reset. **indicates the value upon power-on reset. not reset with a stop mode recovery. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 29 t8 enable this field enables t8 when set (written) to 1. single/modulo-n when set to 0 (modulo-n), the counter reloads the initial value when the terminal count is reached. when set to 1 (single- pass), the counter stops when the termi- nal count is reached. timeout this bit is set when t8 times out (terminal co unt reached). to reset this bit, write a 1 to its location. writing a 1 is the only way to reset the terminal count status condition. reset this bit before using/enabling the counter/timers. the first clock of t8 might not have complete clock width and can occur any time when enabled. ensure to manipulate ctr0, bit 5 and ctr1, bits 0 and 1 (demodulation mode) when using the or or and commands. these instructions use a read-modify-write sequence in which the current status from the ctr0 and ctr1 registers is ored or anded with the designated value and then written back into the registers. t8 clock these bits define the frequency of the input signal to t8. caution: note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 30 capture_int_mask set this bit to allow an interrupt when data is captured into either lo8 or hi8 upon a positive or negative edge detection in demodulation mode. counter_int_mask set this bit to allow an interrupt when t8 has a timeout. p34_out this bit defines whether p34 is used as a normal output pin or the t8 output. t8 and t16 common functionsctr1(0d)01h this register controls the functions in common with the t8 and t16. table 8 lists and briefly describes the fields for this register. table 8. ctr1(0d)01h t8 and t16 common functions field bit position value description mode 7------- r/w 0* 1 transmit mode demodulation mode p36_out/ demodulator_input -6------ r/w 0*1 0* 1 transmit modeport output t8/t16 output demodulation mode p31 p20 t8/t16_logic/ edge _detect --54---- r/w 00** 01 10 11 00** 01 10 11 transmit modeand or nor nand demodulation mode falling edge rising edge both edges reserved downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 31 mode if the result is 0, the counter/timers are in transmit mode; otherwise, they are in demodulation mode. p36_out/demodulator_input in transmit mode, this bit defines whet her p36 is used as a normal output pin or the combined output of t8 and t16. in demodulation mode, this bit defines whether the input signal to the counter/timers is from p20 or p31. if the input signal is from port 31, a capture event may also generate an irq2 interrupt. to prevent generating an irq2, either disable the irq2 interrupt by clearing its imr bit d2 or use p20 as the input. transmit_submode/ glitch_filter ----32-- r/w 0001 10 11 00 01 10 11 transmit mode normal operation ping-pong mode t16_out = 0 t16_out = 1 demodulation mode no filter 4 sclk cycle 8 sclk cycle reserved initial_t8_out/ rising edge ------1- r/wr w 01 0 1 0 1 transmit mode t8_out is 0 initially t8_out is 1 initially demodulation mode no rising edge rising edge detected no effect reset flag to 0 initial_t16_out/ falling_edge -------0 r/wr w 01 0 1 0 1 transmit mode t16_out is 0 initially t16_out is 1 initially demodulation mode no falling edge falling edge detected no effect reset flag to 0 *default at power-on reset. **default at power-on reset. not reset with a stop mode recovery. table 8. ctr1(0d)01h t8 and t16 common functions (continued) field bit position value description downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 32 t8/t16_logic/edge _detect in transmit mode, this field defines how the outputs of t8 and t16 are com- bined (and, or, nor, nand). in demodulation mode, this field defines which edge should be detected by the edge detector. transmit_submode/glitch filter in transmit mode, this field defines whether t8 and t16 are in the ping-pong mode or in independent normal operation mode. setting this field to normal operation mode terminates the ping-pong mode operation. when set to 10, t16 is immediately forced to a 0; a setting of 11 forces t16 to output a 1. in demodulation mode, this field defines t he width of the glitch that must be fil- tered out. initial_t8_out/rising_edge in transmit mode, if 0, the output of t8 is set to 0 when it starts to count. if 1, the output of t8 is set to 1 when it starts to count. when the counter is not enabled and this bit is set to 1 or 0, t8_out is set to the opposite state of this bit. this ensures that when the clock is enabled, a transition occurs to the initial state set by ctr1, d1. in demodulation mode, this bit is set to 1 when a rising edge is detected in the input signal. in order to reset the mode, a 1 should be written to this location. initial_t16 out/falling _edge in transmit mode, if it is 0, the output of t16 is set to 0 when it starts to count. if it is 1, the output of t16 is set to 1 when it starts to count. this bit is effective only in normal or ping-pong mode (ctr1, d3; d2). when the counter is not enabled and this bit is set, t16_out is set to the opposite state of this bit. this ensures that when the clock is enabled, a transition occurs to the initial state set by ctr1, d0. in demodulation mode, this bit is set to 1 when a falling edge is detected in the input signal. in order to reset it, a 1 must be written to this location. modifying ctr1 (d1 or d0) while the counters are enabled causes unpredictable output from t8/16_out. ctr2 counter/timer 16 control registerctr2(d)02h table 9 on page 33 lists and briefly describes the fields for this register. note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 33 t16_enable this field enables t16 when set to 1. single/modulo-n in transmit mode, when set to 0, the counter reloads the initial value when it reaches the terminal count. when set to 1, the counter stops when the terminal count is reached. table 9. ctr2(d)02h: counter/timer16 control register field bit position value description t16_enable 7------- rw 0*1 0 1 counter disabled counter enabled stop counter enable counter single/modulo-n -6------ r/w 0*1 0 1 transmit mode modulo-n single pass demodulation mode t16 recognizes edge t16 does not recognize edge time_out --5----- rw 0**1 0 1 no counter timeout counter timeout occurred no effect reset flag to 0 t16 _clock ---43--- r/w 00** 0110 11 sclksclk/2 sclk/4 sclk/8 capture_int_mask -----2-- r/w 0** 1 disable data capture int. enable data capture int. counter_int_mask ------1- r/w 0* 1 disable timeout int. enable timeout int. p35_out -------0 r/w 0* 1 p35 as port output t16 output on p35 *indicates the value upon power-on reset. **indicates the value upon power-on reset. not reset with a stop mode recovery. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 34 in demodulation mode, when set to 0, t16 captures and reloads on detection of all the edges. when set to 1, t16 captures and detects on the first edge but ignores the subsequent edges. for details, see the description of t16 demodulation mode on page 42. time_out this bit is set when t16 times out (terminal count reached). to reset the bit, write a 1 to this location. t16_clock this bit defines the frequency of the input signal to counter/timer16. capture_int_mask this bit is set to allow an interrupt when data is captured into lo16 and hi16. counter_int_mask set this bit to allow an interrupt when t16 times out. p35_out this bit defines whether p35 is used as a normal output pin or t16 output. ctr3 t8/t16 control registerctr3(d)03h table 10 lists and briefly describes the fields for this register. this register allows the t 8 and t 16 counters to be synchronized. table 10. ctr3 (d)03h: t8/t16 control register field bit position value description t 16 enable 7------- rr w w 0**1 0 1 counter disabled counter enabled stop counter enable counter t 8 enable -6------ rr w w 0**1 0 1 counter disabled counter enabled stop counter enable counter sync mode --5----- r/w 0* 1 disable sync mode enable sync mode downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 35 counter/timer functional blocks input circuit the edge detector monitors the input signal on p31 or p20. based on ctr1 d5C d4, a pulse is generated at the pos edge or neg edge line when an edge is detected. glitches in the input signal t hat have a width less than specified (ctr1 d3, d2) are filtered out (see figure 15 ). figure 15.glitch filter circuitry t8 transmit mode before t8 is enabled, the output of t8 depends on ctr1, d1. if it is 0, t8_out is 1; if it is 1, t8_out is 0 (see figure 16 on page 36). reserved ---43210 rw 1x always reads 11111 no effect *indicates the value upon power-on reset. **indicates the value upon power-on reset. not reset with a stop mode recovery. table 10. ctr3 (d)03h: t8/t16 control register (continued) field bit position value description mux glitch filter edge detector p31p20 pos edge neg edge ctr1 d5,d4 ctr1 d6 ctr1 d3, d2 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 36 figure 16.transmit mode flowchart set timeout status bit (ctr0 d5) and generate timeout_int if enabled set timeout status bit (ctr0 d5) and generate timeout_int if enabled t8 (8-bit) transmit mode no t8_enable bit set ctr0, d7 yes ctr1, d1 value reset t8_enable bit 0 1 load tc8l reset t8_out load tc8h set t8_out enable t8 no t8_timeout yes single pass single modulo-n t8_out value 0 enable t8 no t8_timeout yes pass? load tc8h set t8_out load tc8l reset t8_out 1 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 37 when t8 is enabled, the output t8_out switches to the initial value (ctr1, d1). if the initial value (ctr1, d1) is 0, tc8l is loaded; otherwise, tc8h is loaded into the counter. in single-pass mode (ctr0, d6), t8 counts down to 0 and stops, t8_out toggles, the timeout status bit (ctr0, d5) is set, and a timeout interrupt can be generated if it is enabled (ctr0, d1). in modulo-n mode, upon reaching terminal count, t8_out is toggled, but no interrupt is generated. from that point, t8 loads a new count (if the t8_out level now is 0), tc8l is loaded; if it is 1, tc8h is loaded. t8 counts down to 0, toggles t8_out, and sets the timeout sta- tus bit (ctr0, d5), thereby generating an interrupt if enabled (ctr0, d1). one cycle is thus completed. t8 then loads from tc8h or tc8l according to the t8_out level and repeats the cycle. see figure 17 . figure 17.8-bit counter/timer circuits you can modify the values in tc8h or tc8l at any time. the new values take effect when they are loaded. to ensure known operation do not write these registers at the time the values are to be loaded into the counter/timer. ctr0 d1 negative edge positive edge z8 data bus irq4 ctr0 d2 sclk z8 data bus ctr0 d4, d3 clock t8_out lo8 tc8h tc8l clockselect 8-bit counter t8 hi8 caution: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 38 an initial count of 1 is not allowed (a non-function occurs). an initial count of 0 causes tc8 to count from 0 to ffh to feh . the letter h denotes hexadecimal values. transition from 0 to ffh is not a timeout condition. using the same instructions for stopping the counter/timers and setting the status bits is not recommended. two successive commands are necessary. first, the counter/timers must be stopped. second, the status bits must be reset. these commands are required because it takes one counter/timer clock interv al for the initiated event to actually occur. see figure 18 and figure 19 . figure 18. t8_out in single-pass mode figure 19. t8_out in modulo-n mode note: caution: tc8h counts counter enable command; t8_out switches to its initial value (ctr1 d1) t8_out toggles; timeout interrupt counter enable command; t8_out switches to its initial value (ctr1 d1) timeout interrupt timeout interrupt t8_out t8_out toggles tc8l tc8h tc8h tc8l tc8l ... downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 39 t8 demodulation mode you must program tc8l and tc8h to ffh . after t8 is enabled, when the first edge (rising, falling, or both depending on ctr1, d5; d4) is detected, it starts to count down. when a subsequent edge (rising, falling, or both depending on ctr1, d5; d4) is detected during counting, the current value of t8 is complemented and put into one of the capture registers. if it is a positive edge, data is put into lo8; if it is a negative edge, data is put into hi8. from that point, one of the edge detect status bits (ctr1, d1; d0) is set, and an interrupt can be generated if enabled (ctr0, d2). meanwhile, t8 is loaded with ffh and starts counting again. if t8 reaches 0, the timeout status bit (ctr0, d5) is set, and an interrupt can be generated if enabled (ctr0, d1). t8 then continues counting from ffh (see figure 20 and figure 21 ). figure 20.demodulation mode count capture flowchart t8 (8-bit) count capture t8 enable (set by user) no yes edge present what kind of edge t8 hi8 no yes negative ffh t8 positive t8 lo8 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 40 figure 21. demodulation mode flowchart t8 (8-bit) demodulation mode t8 enable ctr0, d7 no yes ffh ? tc8 first edge present enable tc8 t8_enable bit set edge present t8 timeout set edge present status bit and trigger data capture int. if enabled set timeout status bit and trigger timeout int. if enabled continue counting disable tc8 no yes no yes yes yes no no downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 41 t16 transmit mode in normal or ping-pong mode, the output of t16 when not enabled, is depen- dent on ctr1, d0. if it is a 0, t16_out is a 1; if it is a 1, t16_out is 0. you can force the output of t16 to either a 0 or 1 whether it is enabled or not by program- ming ctr1 d3; d2 to a 10 or 11. when t16 is enabled, tc16h * 256 + tc16l is loaded, and t16_out is switched to its initial value (ctr1, d0). when t16 counts down to 0, t16_out is toggled (in normal or ping-pong mode), an interrupt (ctr2, d1) is generated (if enabled), and a status bit (ctr2, d5) is set (see figure 22 ). figure 22.16-bit counter/timer circuits global interrupts override this function as described in interrupts on page 45. if t16 is in single-pass mode, it is stopped at this point (see figure 23 on page 42). if it is in modulo-n mode, it is loaded with tc16h * 256 + tc16l, and the counting continues (see figure 24 on page 42). you can modify the values in tc16h and tc16l at any time. the new values take effect when they are loaded. ctr2 d1 negative edge positive edge z8 data bus irq3 ctr2 d2 sclk z8 data bus ctr2 d4, d3 clock t16_out lo16 tc16h tc16l clockselect 16-bit counter t16 hi16 note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 42 do not load these registers at the time the values are to be loaded into the counter/timer to ensure known operation. an initial count of 1 is not allowed. an initial count of 0 causes t16 to count from 0 to ffffh to fffeh . transition from 0 to ffffh is not a timeout condition. figure 23.t16_out in single-pass mode figure 24.t16_out in modulo-n mode t16 demodulation mode you must program tc16l and tc16h to ffh . after t16 is enabled, and the first edge (rising, falling, or both depending on ctr1 d5; d4) is detected, t16 cap- tures hi16 and lo16, reloads, and begins counting. if d6 of ctr2 is 0 when a subsequent edge (rising, falling, or both depending on ctr1, d5; d4) is detected during counting, the current count in t16 is complemented and put into hi16 and lo16. when data is captured, one of the edge detect status bits (ctr1, d1; d0) is set and an interrupt is generated if enabled (ctr2, d2). t16 is loaded with ffffh and starts again. caution: tc16h*256+tc16l counts counter enable command t16_out switches to its initial value (ctr1 d0) t16_out toggles, timeout interrupt tc16h*256+tc16l tc16h*256+tc16l tc16h*256+tc16l t16_out toggles, timeout interrupt t16_out toggles, timeout interrupt counter enable command, t16_out switches to its initial value (ctr1 d0) tc16_out ... downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 43 this t16 mode is generally used to meas ure space time, the length of time between bursts of carrier signal (marks). if d6 of ctr2 is 1 t16 ignores the subsequent edges in th e input signal and continues counting down. a timeout of t8 causes t16 to capture its current value and generate an interrupt if enabled (ctr2, d2). in this case, t16 does not reload and continues counting. if the d6 bit of ctr2 is toggled (by writing a 0 then a 1 to it), t16 captures and reloads on the next edge (rising, falling, or both depending on ctr1, d5; d4), continuing to ignore subsequent edges. this t16 mode generally measures mark time , the length of an active carrier sig- nal burst. if t16 reaches 0, t16 continues counting from ffffh . meanwhile, a status bit (ctr2 d5) is set, and an interrupt timeout can be generated if enabled (ctr2 d1). ping-pong mode this operation mode is only valid in transmit mode. t8 and t16 must be programmed in single-pass mode (ctr0, d6; ctr2, d6), and ping-pong mode must be programmed in ctr1, d3; d2. you can begin the operation by enabling either t8 or t16 (ctr0, d7 or ct r2, d7). for example, if t8 is enabled, t8_out is set to this initial value (ctr1, d1). according to t8_out's level, tc8h or tc8l is loaded into t8. after the terminal count is reached, t8 is disabled, and t16 is enabled. t16_out then switches to its initial value (ctr1, d0), data from tc16h and tc16l is loaded, and t16 starts to count. after t16 reaches the terminal count, it stops, t8 is enabled again, repeating the entire cycle. interrupts can be allowed when t8 or t16 reaches terminal control (ctr0, d1; ctr2, d1). to stop the ping-pong operation, write 00 to bits d3 and d2 of ctr1. see figure 25 . enabling ping-pong operation while the counter/timers are running might cause intermittent counter/timer function. disable note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 44 the counter/timers and reset the status flags before instituting this operation. figure 25.ping-pong mode diagram initiating ping-pong mode first, make sure both counter/timers ar e not running. set t8 into single-pass mode (ctr0, d6), set t16 into single-pass mode (ctr2, d6), and set the ping-pong mode (ctr1, d2; d3). these instructions can be in random order. finally, start ping-pong mode by enabling either t8 (ctr0, d7) or t16 (ctr2, d7). see figure 26 . figure 26.output circuit the initial value of t8 or t16 must not be 1 . if you stop the timer and restart the timer, reload the initial value to avoid an unknown previous value. enable tc8 enable timeout tc16 ping-pong ctr1 d3,d2 timeout t16_out mux ctr1 d3 t8_out p34 and/or/nor/nand logic muxmux mux p35 p36 p34_internal ctr1 d5, d4 p36_internal p35_internal ctr1, d2 ctr0 d0ctr1 d6 ctr2 d0 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 45 during ping-pong mode the enable bits of t8 and t16 (ctr0, d7; ctr2, d7) are set and cleared alter- nately by hardware. the timeout bits (ctr 0, d5; ctr2, d5) are set every time the counter/timers reach the terminal count. timer output the output logic for the timers is displayed in figure 26 on page 44. p34 is used to output t8-out when d0 of ctr0 is set. p35 is used to output the value of ti6- out when d0 of ctr2 is set. when d6 of ctr1 is set, p36 outputs the logic combination of t8-out and t16-out determined by d5 and d4 of ctr1. interrupts the crimzon zlr32300 features six different interrupts (see table 11on page 47). the interrupts are maskable and prioritized (see figure 27 on page 46). the six sources are divided as follows: three sources are claimed by port 3 lines p33C p31, two by the counter/timers (see table 11 on page 47) and one for low-volt- age detection. the interrupt mask register (globally or individually) enables or disables the six interrupt requests. the source for irq is determined by bit 1 of the port 3 mode register (p3m). in digital mode, pin p33 is the source. in analog mode the output of the stop mode recovery source logic is used as the source for the interrupt. see figure 32 on page 54. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 46 figure 27. interrupt block diagram low-voltage detection timer 8 timer 16 interrupt edgeselect imr ipr priority logic irq 5 irq2 irq0 irq1 irq3 irq4 irq5 p31 p32 irq register d6, d7 global interrupt enable interrupt request vector select d1 of p3m register p33 0 1 stop mode recovery source downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 47 when more than one interrupt is pending, priorities are resolved by a programmable priority encoder controlled by the interrupt priority register. an interrupt machine cycle activates when an interrupt request is granted. as a result, all subsequent interrupts are disabled, and the program counter and status flags are saved. the cycle then branches to the program memory vector location reserved for that interrupt. all crimzon zlr32300 interrupts are vectored through locations in the program memory. this memory location and the next byte contain the 16-bit address of the interrupt service routine for that particular interrupt request. to accommodate polled interrupt systems, interrupt inputs are masked, and the interrupt request register is polled to determine which of the interrupt requests require service. an interrupt resulting from an1 is mapped into irq2, and an interrupt from an2 is mapped into irq0. interrupts irq2 and irq0 can be rising, falling, or both edge triggered. you can program these interrupts. the software can poll to identify the state of the pin. programming bits for the interrupt edge select are located in the irq register (r250), bits d7 and d6. the configuration is indicated in table 12. table 11. interrupt types, sources, and vectors name source vector location comments irq0 p32 0,1 external (p32), ris ing, falling edge triggered irq1 p33 2,3 external (p33), falling edge triggered irq2 p31, t in 4,5 external (p31), rising, falling edge triggered irq3 t16 6,7 internal irq4 t8 8,9 internal irq5 lvd 10,11 internal table 12.irq register irq interrupt edge d7 d6 irq2 (p31) irq0 (p32) 00 f f 01 f r 10 r f 11 r / f r / f note: f = falling edge; r = rising edge downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 48 clock the devices on-chip oscillator has a hi gh-gain, parallel-resonant amplifier, for connection to a crystal, ceramic resonator, or any suitable external clock source (xtal1 = input, xtal2 = output). the crystal must be at cut, 1 mhz to 8 mhz maximum, with a series resistance (rs) less than or equal to 100 ? . the on-chip oscillator can be driven with a suitable external clock source. the crystal must be connected across xtal1 and xtal2 using the recommended capacitors from each pin to ground. the typical capacitor value is 10 pf for 8 mhz. also check with the crystal supplier for the optimum capacitance. figure 28.oscillator configuration maxims ir mcu supports crystal, resonator, and oscillator. most resonators have a frequency tolerance of less than 0.5%, which is enough for remote control application. resonator has a very fast startup time, which is around few hundred microseconds. most crystals have a frequency tolerance of less than 50 ppm (0.005%). however, crystal needs longer startup time than the resonator. the large loading capacitance slows down the oscillation startup time. maxim ? suggests not to use more than 10 pf loading capacitor for the crystal. if the stray capacitance of the pcb or the crystal is high, the loading capacitance c1 and c2 must be reduced further to ensure stable oscillation before the t por (power-on reset time is typically 5C6 ms, see table 20 on page 85). for stop mode recovery operation, bit 5 of smr register allows you to select the stop mode recovery delay, which is the t por . if stop mode recovery delay is not selected, the mcu executes instruction immediately after it wakes up from the c1c2 xtal1 xtal2 xtal1 xtal2 crystal c1, c2 = 10 pf * f = 8 mh external clock *note: preliminary value. xtal1 xtal2 ceramic resonator f = 8 mh downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 49 stop mode. if resonator or crystal is used as a clock source then stop mode recovery delay has to be selected (bit 5 of smr = 1). for resonator and crystal oscillator, the os cillation ground must go directly to the ground pin of the microcontroller. the oscillation ground must use the shortest dis- tance from the microcontroller ground pin and it must be isolated from other con- nections. power management power-on reset a timer circuit clocked by a dedicated on-board rc-oscillator is used for the power-on reset timer function. the por time allows v dd and the oscillator circuit to stabilize before instruction execution begins. the por timer circuit is a one-shot timer triggered by one of three conditions: power fail to power ok status, including waking up from v bo standby stop mode recovery (if d5 of smr = 1) wdt timeout the por timer is 2.5 ms minimum. bit 5 of the stop mode register determines whether the por timer is bypassed after stop mode recovery (typical for external clock). halt mode this instruction turns off the internal cpu clock, but not the xtal oscillation. the counter/timers and external interrupts irq0, irq1, irq2, irq3, irq4, and irq5 remain active. the devices are recovered by interrupts, either externally or internally generated. an interrupt request must be executed (enabled) to exit halt mode. after the interrupt service routine, the program continues from the instruction after halt mode. stop mode this instruction turns off the internal cloc k and external crystal oscillation, reduc- ing the standby current to 10 ? a or less. stop mode is terminated only by a reset, such as wdt timeout, por, smr or ex ternal reset. this c ondition causes the processor to restart the application program at address 000ch . to enter stop (or halt) mode, first flush the instruction pipeline to avoid suspending execution in mid-instruction. execute a nop (opcode = ffh ) immediately before the appropri- ate sleep instruction, as follows: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 50 ff nop ; clear the pipeline 6f stop ; enter stop mode or ff nop ; clear the pipeline 7f halt ; enter halt mode port configuration port configuration register the port configuration (pcon) register (see figure 29 ) configures the comparator output on port 3. it is located in the expanded register 2 at bank f, location 00. pcon(fh)00h figure 29. port configuration register (pcon) (write only) comparator output port 3 (d0) bit 0 controls the comparator used in port 3. a 1 in this location brings the compar- ator outputs to p34 and p37, and a 0 releases the port to its standard i/o configu- ration. port 1 output mode (d1) d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 p34, p37 standard output* 1 p34, p37 comparator output port 1 0: open-drain 1: push-pull* port 0 0: open-drain 1: push-pull* reserved (must be 1) *default setting after reset. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 51 bit 1 controls the output mode of port 1. a 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. port 0 output mode (d2) bit 2 controls the output mode of port 0. a 1 in this location sets the output to push-pull, and a 0 sets the output to open-drain. stop mode recovery stop mode recovery register this register selects the clock divide value and determines the mode of stop mode recovery (see figure 30 ). all bits are write only ex cept bit 7, which is read only. bit 7 is a flag bit that is hardware set on the condition of stop recovery and reset by a power-on cycle. bit 6 controls whether a low level or a high level at the xor-gate input (see figure 32 on page 54) is required from the recovery source. bit 5 controls the reset delay after recovery. bits d2, d3, and d4 of the smr regis- ter specify the source of the stop mode recovery signal. bits d0 determines if sclk/tclk are divided by 16 or not. the smr is located in bank f of the expanded register group at address 0bh . smr(0f)0bh d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 off * * 1 on reserved (must be 0) downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 52 figure 30. stop mode recovery register sclk/tclk divide-by-16 select (d0) d0 of the smr controls a divide-by-16 prescaler of sclk/tclk (see figure 31 ). this control selectively reduces device power consumption during normal proces- sor execution (sclk control) and/or halt mode (where tclk sources interrupt logic). after stop mode recovery, this bit is set to a 0. figure 31.sclk circuit stop mode recovery source 000 por only * 001 reserved 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0-3 111 p2 nor 0-7 stop delay 0 off 1 on * * * * stop recovery level * * * 0 low * 1 high stop flag 0 por * 1 stop recovery * * *default setting after reset. * *default setting after reset and stop mode recovery. * * *at the xor gate input. * * * *default setting after reset. recommended to be set to 1 if using a crystal or resonator clock source. sclk tclk smr, d0 2 ? osc 16 ? downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 53 stop mode recovery source (d2, d3, and d4) these three bits of the smr specify the wake-up source of the stop recovery (see figure 32 and table 14). stop mode recovery register 2smr2(f)0dh table 13 lists and briefly describes the fields for this register. table 13. smr2(f)0dh:stop mode recovery register 2* field bit position value description reserved 7------- 0 reserved (must be 0) recovery level -6------ w0 ? 1 low high reserved --5----- 0 reserved (must be 0) source ---432-- w 000 ? 001010 011 100 101 110 111 a. por only b. nand of p23Cp20 c. nand of p27Cp20 d. nor of p33Cp31 e. nand of p33Cp31 f. nor of p33Cp31, p00, p07 g. nand of p33Cp31, p00, p07 h. nand of p33Cp31, p22Cp20 reserved ------10 00 reserved (must be 0) *port pins configured as outputs are ignored as an smr source. ? indicates the value upon power-on reset. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 54 figure 32. stop mode recovery source smr2 d4 d3 d2 100 smr2 d4 d3 d2 111 smr d4d3d2 010 smr d4d3d2 111 smr d4d3d2 101 smr d4d3d2 100 smr d4d3d2 011 smr d4d3d2 000 smr d4d3d2 110 vcc p31 p32 p33 p27 p20 p23 p20 p27 smr2 d4 d3 d2 001 smr2 d4 d3 d2 000 smr2 d4 d3 d2 010 smr2 d4 d3 d2 011 smr2 d4 d3 d2 101 smr2 d4 d3 d2 110 vcc p20 p23 p20 p27 p31 p32 p33 p31 p32 p33 p31 p32 p33 p00 p31 p32 p33 p00 p31 p32 p33 p20 p21 smr d6 smr2 d6 to reset and wdt circuitry (active low) downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 55 any port 2 bit defined as an output drives the corresponding input to the default state. this condition allows the remaining inputs to control the and/or function. see smr2 register on page 56 for other recover sources. stop mode recovery delay select (d5) this bit, if low, disables the t por delay after stop mode recovery. the default configuration of this bit is 1. if the fast wake up is selected, the stop mode recovery source must be kept active for at least 10 tpc. this bit must be set to 1 if using a crystal or resonator clock source. the t por delay allows the clock source to stabilize before executing instructions. stop mode recovery edge select (d6) a 1 in this bit position indicates that a high level on any one of the recovery sources wakes the crimzon zlr32300 from stop mode. a 0 indicates low level recovery. the default is 0 on por. cold or warm start (d7) this bit is read only. it is set to 1 when the device is recovered from stop mode. the bit is set to 0 when the device reset is other than stop mode recovery. table 14. stop mode recovery source smr:432 operation d4 d3 d2 description of action 0 0 0 por and/or external reset recovery 001r e s e r v e d 010p 3 1 t r a n s i t i o n 011p 3 2 t r a n s i t i o n 100p 3 3 t r a n s i t i o n 101p 2 7 t r a n s i t i o n 1 1 0 logical nor of p20 through p23 1 1 1 logical nor of p20 through p27 note: note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 56 stop mode recovery register 2 (smr2) this register determines the mode of stop mode recovery for smr2 (see figure 33 ). smr2(0f)dh figure 33. stop mode recovery register 2 ((0f)dh:d2Cd4, d6 write only) if smr2 is used in conjunction with smr, either of the specified events causes a stop mode recovery. port pins configured as outputs are ignored as an smr or smr2 recovery source. for example, if the nand or p23Cp20 is selected as the recovery source and p20 is configured as an d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop mode reco very source 2 000 por only * 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p2 3, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level * * 0low * 1 high reserved (must be 0) note: if used in conjunction with smr, either of the two specified events causes a stop mode recovery. *default setting after reset. **at the xor gate input. note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 57 output, the remaining smr pins (p23Cp21) form the nand equation. watchdog timer mode watchdog timer mode register (wdtmr) the watchdog timer is a retriggerable one-shot timer that resets the z8 if it reaches its terminal count. the wdt must initially be enabled by executing the wdt instruction. on subsequent executions of the wdt instruction, the wdt is refreshed. the wdt circuit is driven by an on-board rc-oscillator. the wdt instruction affects the zero (z), sign (s), and overflow (v) flags. the por clock source the internal rc-oscillator. bits 0 and 1 of the wdt register control a tap circuit that determines th e minimum timeout period. bit 2 determines whether the wdt is active during halt, and bit 3 determines wdt activity during stop. bits 4 through 7 are reserved (see figure 34 ). this register is accessible only during the first 60 processor cycles (120 xtal clocks) from the execution of the first instruction after power-on reset, watchdog reset, or a stop mode recovery (see figure 33 on page 56). after this point, the register cannot be modified by any means (intentional or otherwise). the wdtmr cannot be read. the register is located in bank f of the expanded register group at address location 0fh . it is organized as displayed in figure 34 . wdtmr(0f)0fh d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc 00 10 ms min. 01* 20 ms min. 10 40 ms min. 11 160 ms min. wdt during halt 0off 1on * wdt during stop 0off 1on * reserved (must be 0) *default setting after reset. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 58 figure 34. watchdog timer mode register (write only) wdt time select (d0, d1) this bit selects the wdt time period. it is configured as indicated in table 15. wdtmr during halt (d2) this bit determines whether or not the wd t is active during halt mode. a 1 indi- cates active during halt. the default is 1. see figure 35 . table 15. watchdog timer time select d1 d0 timeout of internal rc-oscillator 00 1 0 m s m i n . 01 2 0 m s m i n . 10 4 0 m s m i n . 1 1 160 ms min. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 59 figure 35. resets and wdt wdtmr during stop (d3) this bit determines whether or not the wdt is active during stop mode. a 1 indi- cates active during stop. the default is 1. rom selectable options there are seven rom selectable options to choose from based on rom code requirements. these are listed in table 16. - * clr1 and clr2 enable the wdt/por and 18 clock reset timers respectively upon a low-to-high input translation. + from stop mode recovery source stop delay select (smr) 5 clock filter *clr2 18 clock reset clk generator reset wdt tap select por 10 ms 20 ms 40 ms 160 clk *clr1 wdt/por counter chain internalrc oscillator. wdt v dd low operating voltage det. vbo v dd internal reset active high 12-ns glitch filter xtal downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 60 voltage brownout/standby an on-chip voltage comparator checks that the v dd is at the required level for correct operation of the device. reset is globally driven when v dd falls below v bo . a small drop in v dd causes the xtal1 and xtal2 circuitry to stop the crystal or resonator clock. if the v dd is allowed to stay above v ram , the ram content is pre- served. when the power level is returned to above v bo , the device performs a por and functions normally. low-voltage detection low-voltage detection registerlvd(d)0ch voltage detection does not work at stop mode. table 16. rom selectable options port 00C03 pull-ups on/off port 04C07 pull-ups on/off port 10C13 pull-ups on/off port 14C17 pull-ups on/off port 20C27 pull-ups on/off port 3 pull-ups on/off watchdog timer at power-on reset on/off field bit position description lvd 76543--- reserved no effect -----2-- r 1 0* hvd flag set hvd flag reset ------1- r 1 0* lvd flag set lvd flag reset -------0 r/w 1 0* enable vd disable vd *default after por. note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 61 do not modify register p01m while checking a low-voltage condition. switching noise of both ports 0 and 1 together might trigger the lvd flag. voltage detection and flags the voltage detection register (lvd, register 0ch at the expanded register bank 0dh ) offers an option of monitoring the v cc voltage. the voltage detection is enabled when bit 0 of lvd register is set. once voltage detection is enabled, the v cc level is monitored in real time. the flags in the lvd register valid 20 s after voltage detection is enabled. the hvd flag (bit 2 of the lvd register) is set only if v cc is higher than v hvd. the lvd flag (bit 1 of the lvd register) is set only if v cc is lower than the v lvd . when voltage detection is enabled, the lvd flag also trig- gers irq5. the irq bit 5 latches the low voltage condition until it is cleared by instructions or reset. the irq5 interrupt is served if it is enabled in the imr regis- ter. otherwise, bit 5 of irq register is latched as a flag only. if it is necessary to receive an lvd interrupt upon power-up at an operating voltage lower than the low-battery detect threshold, enable interrupts using the enable interrupt (ei) instruction prior to enabling the voltage detection. note: note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 62 expanded register file control registers (0d) the expanded register file control registers (0d) are displayed in figure 36 on page 63 through figure 40 on page 68. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 63 figure 36.tc8 control register ((0d)o0h: read/write except where noted) ctr0(0d)00h d7 d6 d5 d4 d3 d2 d1 d0 0 p34 as port output * 1 timer8 output 0 disable t8 timeout interrupt** 1 enable t8 timeout interrupt 0 disable t8 data capture interrupt** 1 enable t8 data capture interrupt 00 sclk on t8** 01 sclk/2 on t8 10 sclk/4 on t8 11 sclk/8 on t8 r 0 no t8 counter timeout** r 1 t8 counter timeout occurred w 0 no effect w 1 reset flag to 0 0 modulo-n* 1 single pass r 0 t8 disabled * r1 t8 enabled w0 stop t8 w 1 enable t8 *default setting after reset. **default setting after reset. not reset with a stop mode recovery. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 64 ctr1(0d)01h d7 d6 d5 d4 d3 d2 d1 d0 transmit mode* r/w 0 t16_out is 0 initially* 1 t16_out is 1 initially demodulation mode r 0 no falling edge detection r 1 falling edge detection w 0 no effect w 1 reset flag to 0 transmit mode* r/w 0 t8_out is 0 initially* 1 t8_out is 1 initially demodulation mode r 0 no rising edge detection r 1 rising edge detection w 0 no effect w 1 reset flag to 0 transmit mode* 0 0 normal operation* 0 1 ping-pong mode 1 0 t16_out = 0 1 1 t16_out = 1 demodulation mode 0 0 no filter 0 1 4 sclk cycle filter 1 0 8 sclk cycle filter 11reserved transmit mode/t8/t16 logic 0 0 and** 01or 1 0 nor 11nand demodulation mode 0 0 falling edge detection 0 1 rising edge detection 1 0 both edge detection 11reserved transmit mode 0 p36 as port output * 1 p36 as t8/t16_out downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 65 figure 37.t8 and t16 common control functions ((0d)01h: read/write) ensure differentiating the transmit mode from demodulation mode. depending on which of these two modes is operating, the ctr1 bit has different functions. changing from one mode to another cannot be performed demodulation mode 0 p31 as demodulator input 1 p20 as demodulator input transmit/demodulation mode 0 transmit mode * 1 demodulation mode *default setting after reset. **default setting after reset. not reset with a stop mode recovery. ctr1(0d)01h note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 66 without disabling the counter/timers. ctr2(0d)02h figure 38. t16 control register ((0d) 2h: read/write except where noted) d7 d6 d5 d4 d3 d2 d1 d0 0 p35 is port output * 1 p35 is tc16 output 0 disable t16 timeout interrupt* 1 enable t16 timeout interrupt 0 disable t16 data capture interrupt** 1 enable t16 data capture interrupt 0 0 sclk on t16** 0 1 sclk/2 on t16 1 0 sclk/4 on t16 1 1 sclk/8 on t16 r 0 no t16 timeout** r 1 t16 timeout occurs w 0 no effect w 1 reset flag to 0 transmit mode 0 modulo-n for t16* 0 single pass for t16 demodulator mode 0 t16 recognizes edge 1 t16 does not recognize edge r 0 t16 disabled * r 1 t16 enabled w 0 stop t16 w1enable t16 *default setting after reset. **default setting after reset. not reset with a stop mode recovery. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 67 ctr3(0d)03h figure 39. t8/t16 control register (0d)03h: read/write (except where noted) if sync mode is enabled, the first pulse of t8 (carrier) is always synchronized with t16 (demo dulated signal). it can always provide a full carrier pulse. d7 d6 d5 d4 d3 d2 d1 d0 reserved 0 no effect 1 always reads 11111 sync mode 0** disable sync mode 1 enable sync mode t 8 enable 0* counter disabled 1 counter enabled 0 stop counter 1 enable counter t 16 enable 0* counter disabled 1 counter enabled 0 stop counter 1 enable counter *default setting after reset. **default setting after reset. not reset with a stop mode recovery. note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 68 lvd(0d)0ch figure 40. voltage detection register do not modify register p01m while checking a low-voltage condition. switching noise of both ports 0 and 1 together might trigger the lvd flag. d7 d6 d5 d4 d3 d2 d1 d0 voltage detection 0: disable * 1: enable lvd flag (read only) 0: lvd flag reset * 1: lvd flag set hvd flag (read only) 0: hvd flag reset * 1: hvd flag set reserved (must be 0) *default setting after reset. note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 69 expanded register file control registers (0f) the expanded register file control registers (0f) are displayed in figure 41 on page 69 through figure 54 on page 79. pcon(0f)00h figure 41. port configuration register (pcon)(0f)00h: write only) d7 d6 d5 d4 d3 d2 d1 d0 comparator output port 3 0 p34, p37 standard output * 1 p34, p37 comparator output port 1 0: open-drain 1: push-pull* port 0 0: open-drain 1: push-pull * reserved (must be 1) *default setting after reset. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 70 smr(0f)0bh figure 42. stop mode recovery register ((0f)0bh: d6Cd0=write only, d7=read only) d7 d6 d5 d4 d3 d2 d1 d0 sclk/tclk divide-by-16 0 off * 1 on reserved (must be 0) stop mode recovery source 000 por only * * 001 reserved 010 p31 011 p32 100 p33 101 p27 110 p2 nor 0C3 111 p2 nor 0C7 stop delay 0off 1 on * * * * stop recovery level * * * 0 low ** 1 high stop flag 0 por * * * * * 1 stop recovery * * *default setting after reset. * *default setting after reset and stop mode recovery. * * *at the xor gate input. * * * *default setting after reset. recommended to be set to 1 if using a crystal or resonator clock source.not reset with stop mode recovery. * * * * *default setting after power-on reset. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 71 smr2(0f)0dh figure 43. stop mode recovery register 2 ((0f)0dh:d2Cd4, d6 write only) d7 d6 d5 d4 d3 d2 d1 d0 reserved (must be 0) reserved (must be 0) stop mode reco very source 2 000 por only * 001 nand p20, p21, p22, p23 010 nand p20, p21, p22, p2 3, p24, p25, p26, p27 011 nor p31, p32, p33 100 nand p31, p32, p33 101 nor p31, p32, p33, p00, p07 110 nand p31, p32, p33, p00, p07 111 nand p31, p32, p33, p20, p21, p22 reserved (must be 0) recovery level * * 0low 1 high reserved (must be 0) note: if used in conjunction with smr, either of the two specified events causes a stop mode recovery. *default setting after reset. not reset with a stop mode recovery. * *at the xor gate input. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 72 wdtmr(0f)0fh figure 44. watchdog timer register ((0f) 0fh: write only) d7 d6 d5 d4 d3 d2 d1 d0 wdt tap int rc osc 00 10 ms min. 01* 20 ms min. 10 40 ms min. 11 160 ms min. wdt during halt 0off 1on * wdt during stop 0off 1on * reserved (must be 0) *default setting after reset. not reset wit a stop mode recovery. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 73 standard control registers the standard control registers are displayed in figure 45 through figure 54 on page 79. r246p2m(f6h) figure 45. port 2 mode register (f6h: write only) d7 d6 d5 d4 d3 d2 d1 d0 p27Cp20 i/o definition 0 defines bit as output 1 defines bit as input * *default setting after reset. not reset wit a stop mode recovery. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 74 r247p3m(f7h) figure 46. port 3 mode register (f7h: write only) d7 d6 d5 d4 d3 d2 d1 d0 0: port 2 open drain * 1: port 2 push-pull 0= p31, p32 digital mode* 1= p31, p32 analog mode reserved (must be 0) *default setting after reset. not reset wit a stop mode recovery. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 75 r248 p01m(f8h) figure 47.port 0 and 1 mode register (f8h: write only) d7 d6 d5 d4 d3 d2 d1 d0 p00Cp03 mode 0: output 1: input * reserved (must be 0) reserved (must be 1) p17Cp10 mode 0: byte output 1: byte input* reserved (must be 0) p07Cp04 mode 0: output 1: input * reserved (must be 0) *default setting after reset; only p00, p01, an d p07 are available on crimzon zlr32300 20-pin configurations. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 76 r249 ipr(f9h) figure 48.interrupt priority register (f9h: write only) d7 d6 d5 d4 d3 d2 d1 d0 interrupt group priority 000 reserved 001 c > a > b 010 a > b >c 011 a > c > b 100 b > c > a 101 c > b > a 110 b > a > c 111 reserved irq1, irq4, priority (group c) 0: irq1 > irq4 1: irq4 > irq1 irq0, irq2, priority (group b) 0: irq2 > irq0 1: irq0 > irq2 irq3, irq5, priority (group a) 0: irq5 > irq3 1: irq3 > irq5 reserved; must be 0 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 77 r250 irq(fah) figure 49.interrupt request register (fah: read/write) r251 imr(fbh) figure 50.interrupt mask register (fbh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 irq0 = p32 input irq1 = p33 input irq2 = p31 input irq3 = t16 irq4 = t8 irq5 = lvd inter edge p31 ? p32 ? = 00 p31 ? p32 ? = 01 p31 ? p32 ? = 10 p31 ?? p32 ?? = 11 d7 d6 d5 d4 d3 d2 d1 d0 1 enables irq5Cirq0 (d0 = irq0) reserved (must be 0) 0 master interrupt disable * 1 master interrupt enable * * *default setting after reset. * *only by using ei, di instruction; di is required before changing the imr register. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 78 r252 flags(fch) figure 51.flag register (fch: read/write) r253 rp(fdh) figure 52.register pointer (fdh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 user flag f1 user flag f2 half carry flag decimal adjust flag overflow flag sign flag zero flag carry flag d7 d6 d5 d4 d3 d2 d1 d0 expanded register bank pointer working register pointer default setting after reset = 0000 0000 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 functional description 79 r254 sph(feh) figure 53.stack pointer high (feh: read/write) r255 spl(ffh) figure 54.stack pointer low (ffh: read/write) d7 d6 d5 d4 d3 d2 d1 d0 general-purpose register d7 d6 d5 d4 d3 d2 d1 d0 stack pointer low byte (sp7Csp0) downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 electrical characteristics 80 electrical characteristicsabsolute maximum ratings stresses greater than those listed in table 17 might cause permanent damage to the device. this rating is a stress rating only. functional operation of the device at any condition above those indicated in the operational sections of these specifica- tions is not implied. exposure to abso lute maximum rating conditions for an extended period might af fect device reliability. table 17.absolute maximum ratings parameter minimum maximum units notes ambient temperature under bias 0 +70 c storage temperature C65 +150 c voltage on any pin with respect to v ss C0.3 +4.0 v 1 voltage on v dd pin with respect to v ss C0.3 +3.6 v maximum current on input and/or inactive output pin C5 +5 a maximum output current from active output pin C25 +25 ma maximum current into v dd or out of v ss 75 ma 1 this voltage applies to all pins except the following: v dd and reset . downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 electrical characteristics 81 standard test conditions the characteristics listed in this product specification apply for standard test con- ditions as noted. all voltages are referenced to gnd. positive current flows into the referenced pin (see figure 55 on page 81). figure 55.test load diagram capacitance table 18 lists the capacitances. table 18.capacitance parameter maximum input capacitance 12 pf output capacitance 12 pf i/o capacitance 12 pf note: t a = 25 c, v cc = gnd = 0 v, f = 1.0 mhz, unmeasured pins returned to gnd from output under test 150 pf downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 electrical characteristics 82 dc characteristics table 19.dc characteristics t a = 0 c to +70 c symbol parameter v cc minimum typ(7) maximum units conditions notes v cc supply voltage 2.0 3.6 v see notes 5 5 v ch clock input high voltage 2.0-3.6 0.8v cc v cc +0.3 v driven by external clock generator v cl clock input low voltage 2.0-3.6 v ss C0.3 0.5 v driven by external clock generator v ih input high voltage 2.0-3.6 0.7v cc v cc +0.3 v v il input low voltage 2.0-3.6 v ss C0.3 0.2 v cc v v oh1 output high voltage 2.0-3.6 v cc C0.4 v i oh = C0.5 ma v oh2 output high voltage (p36, p37, p00, p01) 2.0-3.6 v cc C0.8 v i oh = C7 ma v ol1 output low voltage 2.0-3.6 0.4 v i ol = 4.0 ma v ol2 output low voltage (p00, p01, p36, p37) 2.0-3.6 0.8 v i ol = 10 ma v offset comparator input offset voltage 2.0-3.6 25 mv v ref comparator reference voltage 2.0-3.6 0 v dd -1.75 v i il input leakage 2.0-3.6 C1 1 ? av in = 0 v, v cc pull-ups disabled r pu pull-up resistance 225 675 k ? v in = 0 v; pullups selected by mask option 75 275 k ? i ol output leakage 2.0-3.6 C1 1 ? av in = 0 v, v cc i cc supply current 2.0 3.6 1.22.2 35 mama at 8.0 mhzat 8.0 mhz 1, 21, 2 i cc1 standby current (halt mode) 2.0 3.6 0.50.8 1.6 2.0 mama v in = 0 v, v cc at 8.0 mhz same as above 1, 2, 6 1, 2, 6 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 electrical characteristics 83 i cc2 standby current (stop mode) 2.0 3.6 2.0 3.6 1.52.1 4.7 7.4 8 1020 30 ? a ? a ? a ? a v in = 0 v, v cc wdt is not running same as above v in = 0 v, v cc wdt is running same as above 33 3 3 i lv standby current (low voltage) 1.0 6 ? a measured at 1.3 v 4 v bo v cc low voltage protection 1.8 2.0 v 8 mhz maximum ext. clk freq. v lvd vcc low voltage detection 2.4 v v hvd vcc high voltage detection 2.7 v notes: 1. all outputs unloaded, inputs at rail. 2. cl1 = cl2 = 100 pf. 3. oscillator stopped. 4. oscillator stops when v cc falls below v bo limit. 5. it is strongly recommended to add a filter capacitor (minimum 0.1 ? f), physically close to vdd and gnd if operating voltage fluctuations are anticipated, such as those resulting from driving an infrared led. 6. comparator and timers are on. interrupt disabled. 7. typical values shown are at 25 c. table 19.dc characteristics (continued) t a = 0 c to +70 c symbol parameter v cc minimum typ(7) maximum units conditions notes downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 electrical characteristics 84 ac characteristics figure 56 on page 84 and table 20 on page 85 describe the ac characteristics. figure 56. ac timing diagram clock stop mode recovery source clock setup 1 22 3 3 t in 7 4 5 6 7 irq n 8 9 11 10 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 electrical characteristics 85 table 20.ac characteristics t a =0 c to +70 c 8.0 mhz no symbol parameter v cc minimum maximum units notes watchdog timer mode register (d1, d0) 1 tpc input clock period 2.0C3.6 121 dc ns 1 2 trc,tfc clock input rise and fall times 2.0C3.6 25 ns 1 3 twc input clock width 2.0C3.6 37 ns 1 4 twtinl timer input low width 2.03.6 100 70 ns 1 5 twtinh timer input high width 2.0C3.6 3tpc 1 6 tptin timer input period 2.0C3.6 8tpc 1 7 trtin,tftin timer input rise and fall timers 2.0C3.6 100 ns 1 8 twil interrupt request low time 2.0 3.6 100 70 ns 1, 2 9 twih interrupt request input high time 2.0C3.6 10tpc 1, 2 10 twsm stop mode recovery width spec 2.0C3.6 12 10tpc ns 3 4 11 tost oscillator start-up time 2.0C3.6 5tpc 4 12 twdt watchdog timer delay time 2.0C3.6 2.0C3.6 2.0C3.6 2.0C3.6 1020 40 160 msms ms ms 0, 0 0, 1 1, 0 1, 1 13 t por power-on reset 2.0C3.6 2.5 10 ms notes: 1.timing reference uses 0.9 v cc for a logic 1 and 0.1 v cc for a logic 0. 2.interrupt request through port 3 (p33Cp31). 3.smr C d5 = 1. 4.smr C d5 = 0. downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 packaging 86 packaging package information for all versions of crimzon zlr32300 is displayed in figure 57 through figure 63 on page 91. figure 57.20-pin pdip package diagram figure 58.20-pin soic package diagram downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 packaging 87 figure 59. 20-pin ssop package diagram downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 packaging 88 figure 60. 28-pin soic package diagram downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 packaging 89 figure 61. 28-pin pdip package diagram downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 packaging 90 figure 62. 28-pin ssop package diagram symbol aa1 b c a2 e millimeter inch min max min max 1.730.05 1.68 0.25 5.20 0.65 typ 0.0910.07 7.65 0.63 1.86 0.0256 typ 0.1310.20 1.737.80 5.30 1.990.21 1.78 0.75 0.0680.002 0.066 0.010 0.205 0.0040.397 0.301 0.025 0.0730.005 0.068 0.209 0.0060.402 0.307 0.030 0.0780.008 0.070 0.015 0.212 0.0080.407 0.311 0.037 0.380.20 10.33 5.38 7.90 0.95 nom nom de h l controlling dimensions: mm leads are coplanar within .004 inches. h c detail a e d 28 15 11 4 seating plane a2 e a q1 a1 b l 0 - 8 detail 'a' downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 packaging 91 figure 63. 48-pin ssop package design contact maxim ? on the actual bonding diagram and coordinate for chip-on-board assembly. controlling dimensions : mm leads are coplanar within .004 inch d e h 1 a2 a e seating plane b 48 25 c detail a detail a 0-8? l 1 2 4 note: downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 ordering information 92 ordering information the following table provides part number, description, and memory size of crim- zon zlr32300. memory size part number description 32 k zlr32300h4832g 48-pin ssop 32 k rom zlr32300h2832g 28-pin ssop 32 k rom zlr32300p2832g 28-pin pdip 32 k rom zlr32300s2832g 28-pin soic 32 k rom zlr32300h2032g 20-pin ssop 32 k rom zlr32300p2032g 20-pin pdip 32 k rom zlr32300s2032g 20-pin soic 32 k rom 24 k zlr32300h4824g 48-pin ssop 24 k rom zlr32300h2824g 28-pin ssop 24 k rom zlr32300p2824g 28-pin pdip 24 k rom zlr32300s2824g 28-pin soic 24 k rom zlr32300h2024g 20-pin ssop 24 k rom zlr32300p2024g 20-pin pdip 24 k rom zlr32300s2024g 20-pin soic 24 k rom 16 k zlr32300h4816g 48-pin ssop 16 k rom 8 k zlr32300h4808g 48-pin ssop 8 k rom 4 k zlr32300h4804g 48-pin ssop 4 k rom development tools zlp128ice01zemg* in-circuit emulator note: *zlp128ice01zemg has been replaced by an improved version, zcrmznice01zemg. zlp323ice01zacg 40-pdip/48-ssop accessory kit zcrmznice01zemg crimzon in-cir cuit emulator zcrmzn00100kitg crimzon in-circu it emulator development kit zcrmznice01zacg 20-pin accessory kit zcrmznice02zacg 40/48-pin accessory kit downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 ordering information 93 for fast results, contact your local maxim sales office for assistance in ordering the part desired. part number description maxim part numbers consist of a number of components, as displayed in figure 64 . the example part number zlr323 00h2832g is a crimzon masked rom product in a 28-pin ssop package, with 32 kb of rom and built with lead- free solder. figure 64. part number description example note: contact www.maxim-ic.com for the die form. z lr32300h 2832g environmental flow g = lead free memory size 32 = 32 kb 24 = 24 kb 16 = 16 kb 8 = 8 kb 4 = 4 kb number of pins in package 48 = 48 pins 40 = 40 pins 28 = 28 pins 20 = 20 pins package type h = ssop p = pdip s = soic product number 32300 product line crimzon rom maxim product prefix memory size part number description downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 index 94 indexnumerics 16-bit counter/timer circuits 41 20-pin dip package diagram 86 20-pin ssop package diagram 87 28-pin dip package diagram 89 28-pin soicpackage diagram 88 28-pin ssop package diagram 90 48-pin ssop package diagram 91 8-bit counter/timer circuits 37 a absolute maximum ratings 80 ac characteristics 84 timing diagram 84 address spaces, basic 1 architecture 1 expanded register file 23 b basic address spaces 1 block diagram, zlp32300 functional 4 c capacitance 81 characteristics ac 84 dc 82 clock 48 comparator inputs/outputs 19 configuration port 0 13 port 1 14 port 2 15 port 3 16 port 3 counter/timer 18 counter/timer 16-bit circuits 41 8-bit circuits 37 brown-out voltage/standby 60 clock 48 demodulation mode count capture flowchart 39 demodulation mode flowchart 40 eprom selectable options 60 glitch filter circuitry 35 halt instruction 49 input circuit 35 interrupt block diagram 46 interrupt types, sources and vectors 47 oscillator configuration 48 output circuit 44 ping-pong mode 43 port configuration register 50 resets and wdt 59 sclk circuit 52 stop instruction 49 stop mode recovery register 52 stop mode recovery register 2 56 stop mode recovery source 54 t16 demodulation mode 42 t16 transmit mode 41 t16_out in modulo-n mode 42 t16_out in single-pass mode 42 t8 demodulation mode 39 t8 transmit mode 35 t8_out in modulo-n mode 38 t8_out in single-pass mode 38 transmit mode flowchart 36 voltage detection and flags 61 watchdog timer mode register 57 watchdog timer time select 58 ctr(d)01h t8 and t16 common functions 30 customer feedback form 98 d dc characteristics 82 demodulation mode count capture flowchart 39 flowchart 40 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 index 95 t16 42 t8 39 description pin 6 e eprom selectable options 60 expanded register file 21 expanded register file architecture 23 expanded register file control registers 68 flag 78 interrupt mask register 77 interrupt priority register 76 interrupt request register 77 port 0 and 1 mode register 75 port 2 configuration register 73 port 3 mode register 74 port configuration register 73 register pointer 78 stack pointer high register 79 stack pointer low register 79 stop-mode recovery register 70 stop-mode recovery register 2 71 t16 control register 66 t8 and t16 common control functions register 65 t8/t16 control register 67 tc8 control register 62 watch-dog timer register 72 ffeatures standby modes 2 functional description counter/timer functional blocks 35 ctr(d)01h register 30 ctr0(d)00h register 28 ctr2(d)02h register 32 ctr3(d)03h register 34 expanded register file 21 expanded register file architecture 23 hi16(d)09h register 27 hi8(d)0bh register 26 l08(d)0ah register 27 l0i6(d)08h register 27 program memory map 21 ram 20 register description 60 register file 25 register pointer 24 register pointer detail 26 smr2(f)0d1h register 35 stack 26 tc16h(d)07h register 27 tc16l(d)06h register 27 tc8h(d)05h register 28 tc8l(d)04h register 28 g glitch filter circuitry 35 h halt instruction, counter/timer 49 i input circuit 35 interrupt block diagram, counter/timer 46 interrupt types, sources and vectors 47 l low-voltage detection register 60 m memory, program 20 modulo-n mode t16_out 42 t8_out 38 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 index 96 o oscillator configuration 48 output circuit, counter/timer 44 p package information 20-pin dip package diagram 86 20-pin ssop package diagram 87 28-pin dip package diagram 89 28-pin soic package diagram 88 28-pin ssop package diagram 90 48-pin ssop package diagram 91 pin configuration 20-pin dip/soic/ssop 6 28-pin dip/soic/ssop 7 40- and 48-pin 8 48-pin ssop 8 pin functions port 0 (p07 - p00) 12 port 0 (p17 - p10) 13 port 0 configuration 13 port 1 configuration 14 port 2 (p27 - p20) 14 port 2 (p37 - p30) 15 port 2 configuration 15 port 3 configuration 16 port 3 counter/timer configuration 18 reset) 19 xtal1 (time-based input 11 xtal2 (time-based output) 11 ping-pong mode 43 port 0 configuration 13 port 0 pin function 12 port 1 configuration 14 port 1 pin function 13 port 2 configuration 15 port 2 pin function 14 port 3 configuration 16 port 3 pin function 15 port 3counter/timer configuration 18 port configuration register 50 power connections 2 power supply 6 program memory 20 map 21 rratings, absolute maximum 80 register 56 ctr(d)01h 30 ctr0(d)00h 28 ctr2(d)02h 32 ctr3(d)03h 34 flag 78 hi16(d)09h 27 hi8(d)0bh 26 interrupt priority 76 interrupt request 77 interruptmask 77 l016(d)08h 27 l08(d)0ah 27 lvd(d)0ch 60 pointer 78 port 0 and 1 75 port 2 configuration 73 port 3 mode 74 port configuration 50 , 73 smr2(f)0dh 35 stack pointer high 79 stack pointer low 79 stop mode recovery 52 stop mode recovery 2 56 stop-mode recovery 70 stop-mode recovery 2 71 t16 control 66 t8 and t16 common control functions 65 t8/t16 control 67 tc16h(d)07h 27 tc16l(d)06h 27 tc8 control 62 tc8h(d)05h 28 tc8l(d)04h 28 voltage detection 68 watch-dog timer 72 register description counter/timer2 ls-byte hold 27 downloaded from: http:///
crimzon ? zlr32300 product specification 19-4623; rev 0; 5/09 index 97 counter/timer2 ms-byte hold 27 counter/timer8 control 28 counter/timer8 high hold 28 counter/timer8 low hold 28 ctr2 counter/timer 16 control 32 ctr3 t8/t16 control 34 stop mode recovery2 35 t16_capture_lo 27 t8 and t16 common functions 30 t8_capture_hi 26 t8_capture_lo 27 register file 25 expanded 21 register pointer 24 detail 26 reset pin function 19 resets and wdt 59 ssclk circuit 52 single-pass mode t16_out 42 t8_out 38 stack 26 standard test conditions 81 standby modes 2 stop instruction, counter/timer 49 stop mode recovery 2 register 56 source 54 stop mode recovery 2 56 stop mode recovery register 52 t t16 transmit mode 41 t16_capture_hi 27 t8 transmit mode 35 t8_capture_hi 26 test conditions, standard 81 test load diagram 81 timing diagram, ac 84 transmit mode flowchart 36 vvcc 6 voltage brown-out/standby 60 detection and flags 61 voltage detection register 68 w watchdog timer mode register watchdog timer mode register 57 time select 58 xxtal1 6 xtal1 pin function 11 xtal2 6 xtal2 pin function 11 downloaded from: http:///
19-4623; rev 0; 5/09 customer support crimzon ? zlr32300 product specification 98 customer support for any comments, detail techni cal questions, or reporting problems, please visit maxims technical support at https://support.ma xim-ic.com/micro . downloaded from: http:///

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